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  <body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h1 class="register-section">VDFSR, Virtual SError Exception Syndrome Register</h1><p>The VDFSR characteristics are:</p><h2>Purpose</h2>
        <p>Provides the syndrome value reported to software on taking a virtual SError interrupt exception to EL1, or on executing an <span class="instruction">ESB</span> instruction at EL1.</p>

      
        <p>When the virtual SError interrupt injected using <a href="AArch32-hcr.html">HCR</a>.VA is taken to EL1 using AArch32, then the syndrome value is reported in <a href="AArch32-dfsr.html">DFSR</a>.{AET, ExT} and the remainder of <a href="AArch32-dfsr.html">DFSR</a> is set as defined by VMSAv8-32. For more information, see <span class="xref">The AArch32 Virtual Memory System Architecture</span>.</p>

      
        <p>If the virtual SError interrupt injected using <a href="AArch32-hcr.html">HCR</a>.VA is deferred by an <span class="instruction">ESB</span> instruction, then the syndrome value is written to <a href="AArch32-vdisr.html">VDISR</a>.</p>
      <h2>Configuration</h2><p>AArch32 System register VDFSR bits [31:0] are architecturally mapped to AArch64 System register <a href="AArch64-vsesr_el2.html">VSESR_EL2[31:0]</a> when the highest implemented Exception level is using AArch64.</p><p>This register is present only when FEAT_RAS is implemented. Otherwise, direct accesses to VDFSR are <span class="arm-defined-word">UNDEFINED</span>.</p>
        <p>If EL2 is not implemented, then VDFSR is <span class="arm-defined-word">RES0</span> from Monitor mode when <a href="AArch32-scr.html">SCR</a>.NS == 1.</p>
      <h2>Attributes</h2>
        <p>VDFSR is a 32-bit register.</p>
      <h2>Field descriptions</h2><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="lr" colspan="16"><a href="#fieldset_0-31_16">RES0</a></td><td class="lr" colspan="2"><a href="#fieldset_0-15_14">AET</a></td><td class="lr" colspan="1"><a href="#fieldset_0-13_13">RES0</a></td><td class="lr" colspan="1"><a href="#fieldset_0-12_12">ExT</a></td><td class="lr" colspan="12"><a href="#fieldset_0-11_0">RES0</a></td></tr></tbody></table><h4 id="fieldset_0-31_16">Bits [31:16]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-15_14">AET, bits [15:14]</h4><div class="field"><p>When a virtual SError interrupt is taken to EL1 using AArch32, <a href="AArch32-dfsr.html">DFSR</a>[15:14] is set to VDFSR.AET.</p>
<p>When a virtual SError interrupt is deferred by an <span class="instruction">ESB</span> instruction, <a href="AArch32-vdisr.html">VDISR</a>[15:14] is set to VDFSR.AET.</p><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-13_13">Bit [13]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-12_12">ExT, bit [12]</h4><div class="field"><p>When a virtual SError interrupt is taken to EL1 using AArch32, <a href="AArch32-dfsr.html">DFSR</a>[12] is set to VDFSR.ExT.</p>
<p>When a virtual SError interrupt is deferred by an <span class="instruction">ESB</span> instruction, <a href="AArch32-vdisr.html">VDISR</a>[12] is set to VDFSR.ExT.</p><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-11_0">Bits [11:0]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><div class="access_mechanisms"><h2>Accessing VDFSR</h2>
        <p>Direct reads and writes of VDFSR are <span class="arm-defined-word">UNDEFINED</span> if EL3 is implemented and using AArch32 in all Secure privileged modes other than Monitor mode.</p>

      
        <p>If EL2 is not implemented, then VDFSR is <span class="arm-defined-word">RES0</span> from Monitor mode when <a href="AArch32-scr.html">SCR</a>.NS == 1.</p>
      <p>Accesses to this register use the following encodings in the System register encoding space:</p><h4 class="assembler">MRC{&lt;c&gt;}{&lt;q&gt;} &lt;coproc&gt;, {#}&lt;opc1&gt;, &lt;Rt&gt;, &lt;CRn&gt;, &lt;CRm&gt;{, {#}&lt;opc2&gt;}</h4><table class="access_instructions"><tr><th>coproc</th><th>opc1</th><th>CRn</th><th>CRm</th><th>opc2</th></tr><tr><td>0b1111</td><td>0b100</td><td>0b0101</td><td>0b0010</td><td>0b011</td></tr></table><p class="pseudocode">
if PSTATE.EL == EL0 then
    UNDEFINED;
elsif PSTATE.EL == EL1 then
    if EL2Enabled() &amp;&amp; !ELUsingAArch32(EL2) &amp;&amp; HSTR_EL2.T5 == '1' then
        AArch64.AArch32SystemAccessTrap(EL2, 0x03);
    elsif EL2Enabled() &amp;&amp; ELUsingAArch32(EL2) &amp;&amp; HSTR.T5 == '1' then
        AArch32.TakeHypTrapException(0x03);
    else
        UNDEFINED;
elsif PSTATE.EL == EL2 then
    R[t] = VDFSR;
elsif PSTATE.EL == EL3 then
    if SCR.NS == '0' then
        UNDEFINED;
    else
        R[t] = VDFSR;
                </p><h4 class="assembler">MCR{&lt;c&gt;}{&lt;q&gt;} &lt;coproc&gt;, {#}&lt;opc1&gt;, &lt;Rt&gt;, &lt;CRn&gt;, &lt;CRm&gt;{, {#}&lt;opc2&gt;}</h4><table class="access_instructions"><tr><th>coproc</th><th>opc1</th><th>CRn</th><th>CRm</th><th>opc2</th></tr><tr><td>0b1111</td><td>0b100</td><td>0b0101</td><td>0b0010</td><td>0b011</td></tr></table><p class="pseudocode">
if PSTATE.EL == EL0 then
    UNDEFINED;
elsif PSTATE.EL == EL1 then
    if EL2Enabled() &amp;&amp; !ELUsingAArch32(EL2) &amp;&amp; HSTR_EL2.T5 == '1' then
        AArch64.AArch32SystemAccessTrap(EL2, 0x03);
    elsif EL2Enabled() &amp;&amp; ELUsingAArch32(EL2) &amp;&amp; HSTR.T5 == '1' then
        AArch32.TakeHypTrapException(0x03);
    else
        UNDEFINED;
elsif PSTATE.EL == EL2 then
    VDFSR = R[t];
elsif PSTATE.EL == EL3 then
    if SCR.NS == '0' then
        UNDEFINED;
    else
        VDFSR = R[t];
                </p></div><hr class="bottom_line"/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">30/03/2023 19:07; 997dd0cf3258cacf72aa7cf7a885f19a4758c3af</p><p class="copyconf">Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.</p></body>
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